The Beginning
Sometimes I ask myself what the heck I am doing with my life… This is one of those times. It all started when I came back from a Japan trip last summer (maybe I’ll talk about that another day). I realized how much I actually cared about owning music. Despite telling myself not to spend too much money, I still ended up with a bunch of CDs from Tower Records and a few doujin music stores. Despite growing up in the streaming age, I really enjoy being able to own the piece of media I love without having to worry about it being taken away from me. I still remember the day Reol’s cover of 劣等上等 was taken off of all the streaming platforms—it was not a great feeling.
However, you may ask, how did any of this lead up to me making a jank MP3 player? So, with my expanding collection of CDs, I ended up with a large collection of rips. To be able to listen to these files, I daily drive an iPod Touch 4th generation. Tired of dealing with garbage iTunes and proprietary BS, I wondered how hard would it be to build my own digital audio player? And so begins our story.
sweetPotet.mp3
Born out of insomnia, sweetPotet.mp3 is my stab at building a rudimentary DAP. It is more of an experiment than an actual product. In fact, this is not meant to be a fancy project. It is more for me to get my feet wet with audio stuff. That’s why I made many specific design decisions to keep the whole project refined but reasonable. I only intend to decode and playback MP3 files from this device, so there really is no need for any fancy Cirrus Logic CS43198 (which iBasso somehow crammed 8 of in a DAP).
The Audio Interface Protocol
I am sure if you have dabbled with Arduino, you would almost certainly have heard of I2C, but have you heard of I2S? (also I don’t know why Philips, now NXP, took down the specifications) Having almost nothing similar other than the name, I2S is a very striaghtforward digital audio protocol designed by Philips. It uses two synchronized clock signals (BCLK and LRCLK) to read in the digital audio data. The left and right channel of the audio is sent alternately based on the LRCLK. I ended up choosing I2S instead of something like Sony’s DSD for its simplicity and also the fact you need to have actual DSD files in order to take advantage of the protocol. Trying to decode MP3 and FLAC to a DSD streaming can often be counterproductive.
Hardware Overview
I ended up going with the STM32F0 series of controllers. It is quite cheap nowadays and also supports I2S, so we don’t need to worry on that end. The STM32 would read data from an SD card with SPI. It would then decode it into a I2S PCM stream for the DAC. The chip chosen for this job is a no-frills audio focused DAC made by Asahi Kasei, AK4432VT. It is a very basic two channel I2S DAC supporting 44.1khz - 192khz 32bit playback. While definitely not audiophile grade, it still has a reasonable 109dB dynamic range. In fact, even this is way overkill for this project. Regardless, the output is finally amplified with two good ol’ trusty NE5532s. I was actually looking for some fancies low noise audio op-amps, but after my friend showed me this article, I decided there’s really no reason to go further than this. Also, don’t forget, I am only intending to decode MP3 with this version of the project.
The Clocking Problem
As mentioned above, I decided to use the STM32F0 series of controllers, the STM32F072RBT6 to be exact. The problem with these is that they don’t have a dedicated PLL for I2S like the STM32F4. This leads to many different possibilities for generating the MCLK, BCLK, and LRCLK needed for the AK4432VT. For most audio DACs using I2S, they require the three signals to be synchronized to ensure audio quality and accuracy. Generating those signals is however a challenge. The MCLK signal is usually in the tens of megahertz range with some being even higher since it needs to be 246 - 512 times the frequency of the audio. After generating the MCLK signal, we need to divide it down to generate BCLK and LRCLK. Initially, I tried to play around with the built in clock system with the STM32, but no matter what I did, I just couldn’t be satisfied with the 2% offset. Off I go learning about PLLs. After exploring several ICs from Renesas and TI, I landed on using the Si5351A from Silicon Labs instead. The more I read about PLLs the more confused I got. From what I understand, no matter how well a PLL is designed, it can never beat a counter in jitter and skew performance. So I decided to call it quits and just use a variable clock generator with a counter-based divider. We will see how this turns out as I have never dealt with anything like this before.
The Next Step and the Stupid Tariff
With all the stuff on the table, I can finally start drawing the schematics and designing the actual board. This will take a while so probably don’t expect an update soon. With the ridiculous tariff looming overhead, however, I need to act fast. It is genuinely frustrating what’s happening right now. Without the access to affordable PCB fabrication, hobby PCBs and projects like this are just simply out of reach for many people. It is what it is in the end of the day and I hope things result themselves one way or another oen day.